As is known, read-only memories of the flash type are arranged into cell matrices which are set up as rows, or word lines, and columns, or bit lines.
Each cell comprises a floating gate transistor which has drain and source terminals as well. A floating gate is formed over a semiconductor substrate and isolated therefrom by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate by means of a dielectric layer, and metallic electrodes are provided to contact the drain, source and control gate in order to have predetermined voltage values applied to the memory cell.
Cells in one word line share the electric line driving their respective control gates, while cells in one bit line have their drain terminals in common.
The state of the memory cells can be sensed, i.e., the information stored therein read, through sensing circuitry.
Circuitry for reading the contents of memory cells in the matrix basically comprises:
an input stage receiving address signals for a byte or memory word to be read; PA1 a row/column decode circuit for selecting the byte of the memory cells to be read; PA1 a read amplifier for sensing the state of the cells in that byte; and PA1 an output stage on which the information contained in the byte is presented after reading.
Each reading cycle is divided into a number of mutually clocked steps by pulses having a predetermined duration. These pulses are derived from a main pulse, known as an ATD (Address Transition Detection) pulse, which detects transitions in the addresses. The ATD signal is generated internally in the memory device each time that a level transition occurs in one of the memory addresses.
The read step itself will be discussed in detail hereinafter, in relation to the read amplifier that is to sense the states of the memory cells.
As those of skill in this field know well, the read amplifier, also called a sense amplifier, is a differential type which compares the current flowing through a cell in the memory matrix and the current flowing through a reference cell, such as a virgin cell.
For this purpose, the sense amplifier uses two current-voltage conversion blocks I/V for converting analog read data to digital.
FIG. 1 of the accompanying drawings shows a sense amplifier 10 in the process of carrying out an unbalanced load read operation, in a conventional manner.
A first input of the sense amplifier is connected to a load which comprises a reference cell 2, which may be the aforementioned virgin cell, and a second input of the amplifier is connected to a load which comprises a cell 4 of the memory matrix.
In the example shown, there is a conversion block 3 which comprises a current mirror consisting of PMOS transistors, of which one, P1, is connected as a diode configuration in a column 5 of the reference cell and has an aspect ratio W/L which is a mirror ratio n times that of the other transistor, P2, connected in a column 6 of the memory matrix.
The current Irif placed by the reference cell on its column 5 is mirrored at a ratio of 1:n onto the matrix column 6. Depending on the state of the memory cell, a greater or lesser amount of the mirrored current will be drawn by the cell, which causes an unbalance to appear at corresponding connection nodes A and B to the inputs of the sense amplifier, thereby allowing the state of the memory cell to be "read".
For flash memories, the sensing circuitry is to meet stringent requirements, which adds other problems to the sense amplifier read circuit design.
For example, the read circuitry incorporated to EPROM memory devices required a full column of reference cells, one reference cell per row in the matrix of memory cells. In this way, differences between the reference cells and the matrix cells, as due to they being differently located within the device, could be minimized. In some cases, as many as two columns of reference cells were employed.
That approach is unsuitable for flash memory devices, wherein an overly increased number of reference cells should be avoided, not to increase the threshold voltage spread any further.
For matrices of flash cells it is much better if a single reference column is shared by all of the outputs, but then the reference current must be carried to all the sectors, and a relatively wide spread ensured for the threshold voltages in order for the verify operations to be carried out effectively upon erasing and programming.
In addition, the reference column should be low in parasitic capacitance, in order to allow for quick powering up of the sensing circuitry from a standby condition.
Furthermore, dynamic reading requires that the input nodes to the sense amplifier be equalized before a read or a verify operation can be performed.
This equalization step would see, on the one side, a single reference column, and on the other, a set of matrix outputs which may number eight or sixteen, according to the number of the sectors.
A high capacitance would, therefore, be needed of the reference node to avoid dependence of the equalization on pattern.
It will be appreciated that the two last-mentioned stipulations are conflicting ones.